1. Field of the Invention
The present invention relates to a driving technology, particularly to a serial transmission driving method.
2. Description of the Related Art
The control unit of an industrial control device normally has a serial transmission interface for communication and control. A serial transmission interface has two differential buses to connect with the serial interfaces of the other control units. One differential bus is normally connected with a plurality of control units. The more the control units, the heavier the equivalent load. Therefore, a serial transmission interface is normally hard to drive too many devices in various applications.
Refer to FIG. 1, wherein two differential buses 10 and 12 are connected with a plurality of components, and wherein a component 30 comprises an interface chip 14, a processor 16, a first optical coupler 24, a second optical coupler 26 and a protection element 15. While the differential bus is connected with a plurality of components, the total load thereof, which is represented by a load capacitor 18, is considerably great. The two differential buses 10 and 12 are respectively connected with a high-voltage terminal VCC and a ground terminal through resistors 20 and 22. In the application of the serial transmission interface, only two optical couplers 24 and 26 are arranged between the processor 16 and the interface chip 14, considering the cost factor. The first optical coupler 24 is used in the receiving terminal (a first terminal) of the interface chip 14. The second optical coupler 26 is used in the control terminals (a second terminal and a third terminal) or the data input terminal (a fourth terminal) of the interface chip 14. Because the second optical coupler 26 is simultaneously applied to the control terminals and the data input terminal, the application thereof is considerably limited. The practical limitation is as follows: the transmitter 28 of the interface chip 14 can only transmit the “0” signal because the fourth terminal is grounded equivalently. The “1” signal must be pulled by the resistors 20 and 22. However, the load capacitor 18 is very great because many components and long lines are attached to the two differential buses 10 and 12. Thus, the resistors 20 and 22 are hard to pull the “1” signal. Therefore, the abovementioned serial transmission interface cannot be used in high-speed transmission but can only be used in low-speed transmission.
Below, the conventional technology where two interface chips 14 and 30 transmit signals mutually is described. Refer to FIG. 2 and FIG. 3. Suppose that the high-voltage terminal is at a voltage of 5V, and that each of resistors 20 and 22 has a resistance of 1000 Ohm, and that the other components result in a load capacitor 18 having a capacitance of 0.1 μF. During signal transmission, let a second terminal and a third terminal of the interface chip 14 receive an input digital signal S having a frequency of 2.5 Hz, and let a fourth terminal be grounded equivalently. Two terminals of the load capacitor 18 are respectively Node A and Node B.
The output terminal of the receiver of the interface chip 30 is Node RO. Because the fourth terminal of the interface chip 14 is grounded, the transmitter 28 of the interface chip 14 can only transmit the “0” signal. In FIG. 3, the top graph shows the input digital signal S; the middle graph shows the signals of Node A and Node B, wherein the solid line represents the voltage of Node A and the dashed line represents the voltage of Node B; the bottom graph shows the signal of Node RO. During the time interval about between 2.5 msec and 2.7 msec, the input digital signal S is a high-level signal, and the transceiver logic of the transmitter 28 is “0”. At this time, the signals of Node A and Node B are respectively shifted to a low-level voltage and a high-level voltage rapidly; the voltage of Node RO is a low-level voltage. At about 2.7 msec, the input digital signal S is shifted from a high-level signal to a low-level signal, whereby the transmitter 28 is switched off. Then, the resistors 20 and 22 are used to pull the voltages of Node A and Node B, whereby the voltages of Node A and Node B are respectively pulled up and down. The voltage of Node RO jumps to a high-level voltage as soon as the voltage of Node A is higher than the voltage of Node B. Theoretically, Node RO cannot receive signals with good quality unless the duty cycle of the voltage of Node RO is 50%. However, the duty cycle of the voltage of Node RO is 22% in fact because the resistors 20 and 22 are used to pull the voltages of Node A and Node B. Therefore, the pulling force is insufficient obviously. Refer to FIG. 4. While the input digital signal S has a frequency of 5 kHz, Node A is unlikely to have a voltage greater than the voltage of Node B. Thus, the duty cycle of the voltage of Node RO becomes 0%, and Node RO cannot receive any signal. In the abovementioned conventional technology, while the load capacitor 18 has a capacitance of 0.1 μF, the system has no chance to receive normal signals unless the maximum frequency of the input digital signal S is less than 2.5 kHz. Even though signals are received in such a case, the signal quality is very poor.
Accordingly, the present invention proposes a serial transmission driving method to overcome the abovementioned problems.